Electronic RAM has evolved over the years from arrays of discrete, electromagnetic “cores” of ferrite material with magnetizing and sensing windings to semiconductor memory technologies in use today. Current-technology RAM cells may be volatile or non-volatile (the latter referred to as NVRAM) to the extent that they lose the integrity of their contents when power supply rails are de-energized or the cell contents are not periodically re-written (“refreshed”). The latter occurs with dynamic RAM (“DRAM”), in widespread use over the past few decades in the computer industry due to its speed, density and low cost. Newer-technology NVRAM including flash memory and ferroelectric RAM (“FeRAM” or “FRAM”) are evolving developmentally in terms of speed, density and cost reduction. The fast evolution of hand-held computing devices including smart phones and tablet computers is a large driving factor in the evolution of NVRAM technologies.
Semiconductor RAM technology has been based largely on memory cells which include capacitance as the basic storage element. Typically a two-dimensional matrix of capacitors or capacitor/transistor pairs forms a memory bit array. A particular capacitor in the array is addressed by row and column driver and/or sense lines. Typically a bit is written by charging the capacitor and the corresponding bit is read by sensing the voltage across the capacitor or by discharging the capacitor and sensing the current flow. In the case of DRAM, a cell capacitor's dielectric material leaks charge quickly after the cell has been written, requiring refresh. In the case of the flash memory type of NVRAM, a high-quality dielectric barrier associated with a floating gate transistor holds electrons pushed across the barrier using a high voltage produced by a charge pump power supply. The charge is maintained indefinitely and thus flash memory is non-volatile at power-off.
In the case of FRAM memory, the capacitor includes a “ferroelectric” fabricated between the plates rather than a dielectric as in the case of a standard capacitor. A characteristic of ferroelectric material such as lead zirconate titanate is that it includes a crystalline lattice of molecules capable of forming and trapping electric dipoles. When the ferroelectric capacitor in an FRAM cell is charged, electric dipoles are aligned in a semi-permanent orientation according to the polarity of a voltage applied across the plates of the capacitor. The dipoles are trapped in that orientation in the crystalline lattice, thus establishing a state in the capacitor that is non-volatile at power-off.
FIG. 1 is a prior-art schematic diagram of a two-transistor, two-capacitor (“2T/TC”) single-bit FRAM storage cell 100. The 2T/2C FRAM architecture and its operation will be described and used in examples hereunder. It is noted, however, that some FRAM arrays may be fabricated using 1T/1C cells. In the case of 2T/2C architecture, the ferroelectric capacitor associated with each half-cell is normally charged to the opposite polarity of the other half-cell capacitor. At read-out, the read signal is the algebraic difference between the voltages created by the opposite charges on the two half-cells. In general, this difference results in a greater read-out voltage margin than would be available from a 1T/1C storage cell. It is also noted that the description that follows uses the terms “negatively charged” and “storing a logical 0” synonymously when referring to the state of a half-cell so charged. Likewise, the description uses the terms “positively charged” and “storing a logical 1” synonymously when referring to the state of a half-cell so charged. This terminology is used for clarity and convenience. However it is noted that referring to a 2T/2C half-cell as storing a logical state is not entirely correct insofar as a half-cell of a 2T/2C FRAM cell stores a charge and the full 2T/2C cell stores the logical state of the cell as interpreted by the sense amplifier as described below.
In general, the 2T/2C cell operates as follows. The cell is prepared for writing a “1” by presenting a “1” (voltage high) at the cell bit line 103 and closing the write switches 104. First, a logical “0” is written to the right half-cell 105. With the right half-cell bit line 108 low from the negated right half-cell driver 112 and the word line 115 active, the plate line 118 is pulsed high. Doing so applies a negative voltage across the right half-cell capacitor 121 and causes dipoles inside its ferroelectric material to be aligned in a “negative” direction. Next, a logical “1” is written to the left half-cell 125 by reverting the plate line 118 back to ground while the left half-cell bit line 130 is driven high by the left half-cell driver 134. Doing so applies a positive voltage across the left half-cell capacitor 140 and causes dipoles inside its ferroelectric material to be aligned in a “positive” direction. A logical “0” is written to the FRAM cell 100 by reversing the polarities of the above-described operations.
A read operation is accomplished by first pre-discharging both half-cell bit lines 108 and 130. The write switches 104 are opened to leave the two half-cell bit lines 108 and 130 floating. The read switches 145 are closed. The word line 115 is enabled and the plate line 118 is pulsed high. The different polarization charges on the two half-cell capacitors 121 and 140 cause the two bit lines 108 and 130 to settle to different voltages. The voltage differential is sensed at the sense amp 150.
For the example described above of a “1” stored in the left half-cell 125 and a logical “0” stored in the right half-cell 105, the read-out operation applies the same polarities to the right half-cell capacitor 121 as written. Doing so results in only a small charge movement to the right-side bit line 108 and the polarity of capacitor 121 remains as charged during the write operation. However, the read operation reverses the polarity of the left half-cell capacitor 140 and results in a larger charge flow to the left-side bit line 130. The sense amp 150 output swings high, to a “1” state, due to the larger signal on the positive input resulting from the polarity reversal at the left half-cell capacitor 140. Thus, the data bit “1” written to the 2T/2C storage cell 100 in the write sequence described above is read out as a “1” as is expected.
FIG. 2 is a prior-art statistical plot showing distribution curves 205 and 210 for bit line signal voltages 215 during read-out for a number 218 of 2T/2C FRAM half-cells. The read-out voltages represented by the distribution curves 205 and 210 correspond, for example, to the voltages seen on the bit lines 108 and 130 of FIG. 1 during read-out. The voltage differential 220 between half-cells bit lines is sensed by the sense amp 150 of FIG. 1 as described above and determines the margin of accuracy of the read-out data. It is noted that, for the capacitor polarization and corresponding logic levels of the half-cells of the example 2T/2C FRAM cell of FIG. 1, the lower-voltage half-cell voltage distribution curve 205 represents negatively charged half-cells storing a logical “0.” The higher-voltage half-cell voltage distribution curve 210 represents positively charged half-cells storing a logical “1.” Of course the logic levels may be reversed in some implementations.
Assume, for example, the sense amp 150 input polarities and the storage of a logical “1” in the storage cell 100 as described with reference to FIG. 1. In that case, the curve 205 represents the right half-cell, the curve 210 represents the left half-cell, and the voltage differential 220 is approximately equal to 1.38V−0.54V=+0.84V. A logical “0” stored in the 2T/2C cell 100 of FIG. 1 would result in a voltage differential 220 of approximately −0.84V. The sense amp 150 typically operates like a voltage comparator in that the output state reflects the polarity of the input voltage differential 220.
U.S. patent application Ser. No. 14/737,247 filed Jun. 11, 2015 discloses generalized structures and methods associated with a memory array capable of storing two bits per storage cell. A read-only (“RO”) bit is imprinted during manufacturing and is accessible post-manufacturing via a special read procedure. The imprinted cell remains capable of normal read-write (“R/W”) operation, however. A memory array including such two bit per cell structures is termed “dual mode memory array.” U.S. patent application Ser. No. 14/737,247 filed Jun. 11, 2015 is incorporated herein by reference in its entirety.